Solid-state imaging device

ABSTRACT

A solid-state imaging device for enlarging an operating margin of a pixel portion and achieving complete transfer of a signal charge by using a plurality of power supply voltages, wherein a plurality of power supplies having different power supply voltage values are supplied to portions of a semiconductor chip  1 . For example, as a first power supply system, a first digital power supply voltage (DVDD 1 ) is supplied from a power supply terminal  45 , a first digital ground voltage (DVSS 1 ) is supplied from a power supply terminal  46 , a second digital power supply voltage (DVDD 2 ) is supplied from a power supply terminal  47 , a second digital ground voltage (DVSS 2 ) is supplied from a power supply terminal  48 , a third digital power supply (DVDD 3 ) is supplied from a power supply terminal  49 , and a third digital ground voltage (DVSS 3 ) is supplied from a power supply terminal  50 , and as a second power supply system, a first analog power supply voltage (AVDD 1 ) is supplied from a power supply terminal  40 , a first analog ground voltage (AVSS 1 ) is supplied from a power supply terminal  41 , a second analog power supply voltage (AVDD 2 ) is supplied from a power supply terminal  42 , and a second analog ground voltage (AVSS 2 ) is supplied from a power supply terminal  43.

This application claims priority to Japanese Patent Application NumberJP2002-102046, filed Apr. 4, 2002 which is incorporated herein byreference.

TECHNICAL FIELD

The present invention relates to an amplification type (CMOS sensortype) solid-state imaging device having a pixel portion comprised of aplurality of unit pixels and a peripheral circuit portion forcontrolling the pixel portion, more particularly relates to animprovement of a power supply circuit of the same.

BACKGROUND ART

Conventionally, an amplification type (CMOS sensor type) solid-stateimaging device for example as shown in FIG. 1 to FIG. 7 has been known.Below, an explanation will be given of the configuration and operationof the conventional example using these drawings.

FIG. 1 is a schematic plan view of an example of the configuration ofthe conventional solid-state imaging device.

This solid-state imaging device is comprised of a semiconductor chip 1on which a pixel portion 2 having a large number of unit pixels arrangedin a two-dimensional array, a timing generator portion 3 for generatingvarious types of timing signals, an output column portion 4 such as acolumn CDS for performing correlated double sampling (CDS) for eachpixel column (column) of the unit pixels or a column AD for performingA/D conversion, a horizontal drive portion 5 for selecting and drivingthis output column portion 4 in a horizontal direction, a vertical driveportion 6 for selecting and driving each pixel row, a signal processingportion (DSP) 7 for performing signal processing with respect to pixelsignals read out from the pixel portion 2, etc. formed thereon.

This solid-state imaging device is driven by two power supply systems ofa first power supply system (hereinafter, referred to as a “digitalpower supply” for convenience) and a second power supply system(hereinafter, referred to as an “analog power supply” for convenience)as the power supply system. The semiconductor chip 1 has a power supplyterminal 8 supplied with a digital power supply voltage DVDD as thefirst power supply system, a power supply terminal 9 supplied with adigital ground voltage DVSS, a power supply terminal 10 supplied with ananalog power supply voltage AVDD as the second power supply system, anda power supply terminal 11 supplied with an analog ground voltage AVSS.

In this way, in the conventional solid-state imaging device, the digitalpower supply voltage (DVDD) and the analog power supply voltage (AVDD)have the same voltage value (for example 1.8V, 2.5V, or 3.3V), thereforeeven if a plurality of electrode pads PAD are arranged on thesemiconductor chip 1, one type of power supply voltage is supplied fromthe outside of the chip 1, and it is operating with a single powersupply voltage.

FIG. 2 is a cross-sectional view of a stack structure of the pixelportion 2 of the conventional example shown in FIG. 1.

As illustrated, a silicon substrate 12 has a P-well 13 formed on it.This P-well 13 has an element isolation area (LOCOS element isolation inthe present example, but sometimes STI etc.) 14, a power supply area(AVDD) 15, a reset gate (Reset) 16 of a reset transistor, a chargedetection unit 17 referred to as a floating diffusion (FD) portion, atransfer transistor (transfer gate TG) 18 for transferring a signalcharge of a photodiode 23 to the FD portion 17, a P+ type lightreceiving layer 19 and an N-type photo-electric conversion layer 20configuring the photodiode 23, etc. formed on it.

In such a solid-state imaging device, with each succeeding generation ofsemiconductor process, the used power supply voltage has become smaller,for example, 3.3V in a 0.35 μm process, 2.5V in a 0.25 μm process, and1.8V in a 0.18 μm process.

On the other hand, the solid-state imaging device is a mixedanalog-digital device requiring a circuit portion driven by a secondpower supply system (hereinafter referred to as an “analog circuitportion”) and a circuit portion driven by the first power supply system(hereinafter referred to as a “digital circuit portion”). Accordingly,the above digital circuit portion operates even if the power supplyvoltage is lowered. However, a reduction of voltage of the analogcircuit portion is difficult.

Especially, for the pixel portion 2 in the analog circuit portion, thesignal charge (Qsig) must be completely transferred from the photodiode23 to the charge detection unit 17, so reduction of the voltage isdifficult.

FIG. 3 to FIG. 7 are explanatory views of potential levels correspondingto the cross-sectional view shown in FIG. 2, wherein the ordinatescorrespond to a potential level PTN (V), and the abscissas correspond toa location for forming each element on the substrate surface of FIG. 2.

Below, an explanation will be given of a conventional read operation ofthe signal charge.

First, in FIG. 3, while the signal charge 24 is being stored in thephotodiode (PD) 23, a drain terminal 15 of the reset transistor 16becomes the power supply voltage AVDD1. In the illustrated example,AVDD1=2.5V (indicated by 26 in the figure). At this time, the gatevoltage (ΦTG) of the transfer gate 18 is 0V.

Further, the potential level (ΦR) when the reset transistor 16 is “OFF”is for example about 1V (indicated by 27 in the figure). This resettransistor 16 becomes a deep depletion type transistor.

Next, as shown in FIG. 4, the gate of the reset transistor 16 is madethe “ON” state. That is, ΦR=2.5V. Then, the potential under the gate ofthe reset transistor 16 is deeply reset (reset to 3V in the illustratedexample) (indicated by 28 in the figure), and the FD potential becomesthe same potential (indicated by 26 in the figure) as the power supplyvoltage 15 (AVDD1=2.5V). That is, the FD potential is reset to the powersupply voltage by using the deep depletion type transistor for the resettransistor 16.

Next, FIG. 5 shows the potential when making the reset transistor 16 the“OFF” state, and the FD potential is the same as the potential of AVDD1as it is. The FD potential actually becomes slightly smaller thanAVDD1=2.5V due to a parasitic capacitance with the gate of the resettransistor 16 (indicated by 25 in the figure).

Further, FIG. 6 shows the potential when reading. By applying an “ON”voltage to the transfer gate 18, the signal charge (Qsig) 24 is read outto the FD portion 17.

Here, most of the signal charge (Qsig1) of the signal charge (Qsig) 24is read out to the FD portion 17, but part of the signal charge (Qsig2)29 remains in the photodiode 23.

These remaining signal charge becomes a residual image and causes theimage characteristics to deteriorate.

Here, the cause of the occurrence of a residual image is that thevoltage applied to the transfer gate 18 is relatively small, so apotential barrier 31 is generated under the gate of the transfer gate 18and the signal charge of the photodiode 23 cannot be completely readout.

In this way, in the conventional amplification type solid-state imagingdevice, the smaller the voltage driving the pixel portion, the largerthe possibility of the occurrence of a residual image and the greaterthe deterioration of the image quality.

FIG. 7 shows the potential after making the transfer gate 18 “OFF”. Asillustrated, the gate voltage (ΦTG) of the transfer gate 18 becomes 0V(indicated by 32 in the figure), and a signal charge (Qsig2) 29 remainsin the photodiode 23.

As described above, in the conventional amplification type solid-stateimaging device, the voltage driving the pixel portion is small, so thesignal charge of the photodiode cannot be completely read out. Thisbecomes the cause of occurrence of a residual image.

Further, the problem arises that due to such a background, a largeoperating margin of the pixel portion cannot be obtained. Further, theproblem arises that the structure etc. of the pixel portion becomesrestricted, the production process becomes troublesome, and a largepower supply voltage becomes necessary.

DISCLOSURE OF THE INVENTION

A first object of the present invention is to provide a solid-stateimaging device able to use a plurality of power supply voltages toenlarge an operating margin of the pixel portion by and achieve completetransfer of the signal charge.

A second object of the present invention is to provide a solid-stateimaging device able to realize a reduction of the number of masks in theproduction process and a shortening of the process steps.

To attain the above objects, a first aspect of the present invention isa solid-state imaging device having a pixel portion comprised of aplurality of unit pixels and a peripheral circuit portion forcontrolling the pixel portion, wherein the peripheral circuit operatessupplied with a first power supply voltage of a first power supplysystem and the pixel portion operates supplied with a second powersupply voltage having a value different from that of the first powersupply voltage of the second power supply system, comprising a firstpower supply inputting means for receiving as input the first powersupply voltage of the first power supply system from the outside and asecond power supply inputting means for receiving as input the secondpower supply voltage of the second power supply system from the outsideand supplying the same to the pixel portion.

Further, a second aspect of the present invention is a solid-stateimaging device having a pixel portion comprised of a plurality of unitpixels and a peripheral circuit portion for controlling the pixelportion, wherein the peripheral circuit operates supplied with a firstpower supply voltage and the pixel portion operates supplied with asecond power supply voltage having a value different from that of thefirst power supply voltage, comprising a power supply inputting meansfor receiving as input a power supply voltage of a single level from theoutside and a level shifting means for converting the level of the powersupply voltage received as input by the power supply inputting means tothe first power supply voltage and/or second power supply voltage,wherein the first power supply voltage generated by the level shiftingmeans is selectively supplied to the peripheral circuit portion, and thegenerated second power supply voltage is selectively supplied to thepixel portion.

In the solid-state imaging device of the present invention, since aplurality of different power supply voltages are input from the outside,and the plurality of power supply voltages are selectively supplied tothe pixel portion and the peripheral circuit portion, by using theplurality of power supply voltages, setting the optimum powerconsumption in each portion becomes possible. Especially, the secondpower supply voltage required for the pixel portion can be effectivelyset.

Accordingly, the operating margin of each portion is enlarged, the powerconsumption of the circuit portion including the pixel portion can bereduced, and further it becomes possible to achieve complete transfer ofthe signal charge in the pixel portion.

Further, change of the threshold value Vth of the transistor, which isusually selectively set at the ion implantation mask, becomesunnecessary, so the number of masks at the time of the ion implantationwork can be greatly reduced, and shortening of the process steps can berealized.

Further, in the solid-state imaging device of the present invention, aplurality of different power supply voltages are generated from thepower supply voltage from the outside by using the level shifting means,and the plurality of different power supply voltages are selectivelysupplied to the pixel portion and the peripheral circuit portion,therefore by using the plurality of power supply voltages, setting theoptimum power consumption for each portion becomes possible. Especiallythe second power supply voltage required for the pixel portion can beeffectively set.

Accordingly, the operating margin of each portion is enlarged, the powerconsumption of the circuit portion including the pixel portion can bereduced, and further it becomes possible to achieve a complete transferof the signal charges in the pixel portion.

Further, change of the threshold value Vth of the transistor, which isusually selectively set at the ion implantation mask, becomesunnecessary, so the number of masks at the ion implantation work can begreatly reduced, and shortening of the process steps can be realized.

BRIEF DESCRIPTION OF THE INVENTION

FIG. 1 is a schematic plan view of an example of the configuration of aconventional amplification type solid-state imaging device.

FIG. 2 is a cross-sectional view of a stack structure of a pixel portionin the conventional example shown in FIG. 1.

FIG. 3 is an explanatory view of a transition of a potential level ofthe conventional example shown in FIG. 1.

FIG. 4 is an explanatory view of the transition of the potential levelof the conventional example shown in FIG. 1.

FIG. 5 is an explanatory view of the transition of the potential levelof the conventional example shown in FIG. 1.

FIG. 6 is an explanatory view of the transition of the potential levelof the conventional example shown in FIG. 1.

FIG. 7 is an explanatory view of the transition of the potential levelof the conventional example shown in FIG. 1.

FIG. 8 is a schematic plan view of an example of the configuration of anamplification type solid-state imaging device according to a firstembodiment of the present invention.

FIG. 9 is a schematic plan view of an example of the configuration of anamplification type solid-state imaging device according to a secondembodiment of the present invention.

FIG. 10 is a schematic plan view of an example of the configuration ofan amplification type solid-state imaging device according to a thirdembodiment of the present invention.

FIG. 11 is a block diagram of an example of configurations of a unitpixel and a vertical drive portion in a fourth embodiment of the presentinvention.

FIGS. 12A to 12C are timing charts of operation timings of theembodiment shown in FIG. 11.

FIG. 13 is a cross-sectional view of a stack structure of the pixelportion of the embodiment shown in FIG. 11.

FIG. 14 is an explanatory view of the transition of the potential levelof the embodiment shown in FIG. 11.

FIG. 15 is an explanatory view of the transition of the potential levelof the embodiment shown in FIG. 11.

FIG. 16 is an explanatory view of the transition of the potential levelof the embodiment shown in FIG. 11.

FIG. 17 is an explanatory view of the transition of the potential levelof the embodiment shown in FIG. 11.

FIG. 18 is an explanatory view of the transition of the potential levelof the embodiment shown in FIG. 11.

FIG. 19 is a block diagram of an example of the configurations of theunit pixel and the vertical drive portion in a fifth embodiment of thepresent invention.

FIGS. 20A to 20C are timing charts of operation timings of theembodiment shown in FIG. 19.

FIG. 21 is a block diagram of an example of the configurations of theunit pixel and the vertical drive portion in a sixth embodiment of thepresent invention.

FIGS. 22A to 22E are timing charts of operation timings of theembodiment shown in FIG. 21.

FIG. 23 is an explanatory view of the transition of the potential levelof the embodiment shown in FIG. 21.

FIG. 24 is an explanatory view of the transition of the potential levelof the embodiment shown in FIG. 21.

FIG. 25 is an explanatory view of the transition of the potential levelof the embodiment shown in FIG. 21.

FIG. 26 is an explanatory view of the transition of the potential levelof the embodiment shown in FIG. 21.

FIG. 27 is an explanatory view of the transition of the potential levelof the embodiment shown in FIG. 21.

FIG. 28 is an explanatory view of the transition of the potential levelof the embodiment shown in FIG. 21.

FIG. 29 is a block diagram of an example of the configuration of theunit pixel in a seventh embodiment of the present invention.

FIGS. 30A to 30F are timing charts of operation timings of theembodiment shown in FIG. 29.

FIG. 31 is a block diagram of an example of the configuration of theunit pixel in an eighth embodiment of the present invention.

FIGS. 32A to 32E are timing charts of operation timings of theembodiment shown in FIG. 31.

FIG. 33 is a block diagram of an example of the configuration of theunit pixel in a ninth embodiment of the present invention.

FIG. 34 is a schematic cross-sectional view of an example of the stackstructure of a level shift circuit shown in FIG. 33.

BEST MODE FOR WORKING THE INVENTION

Below, an explanation will be given of embodiments of a solid-stateimaging device according to the present invention.

The solid-state imaging device according to the embodiment of thepresent invention is for solving the problems of a residual image etc.by supplying power supply voltages of a plurality of levels from theoutside of the semiconductor chip or by providing a boosting means inthe semiconductor chip and thereby applying a high voltage to the pixelportion, applying a low voltage to the peripheral circuit portion, andresetting the FD portion with a high voltage so as to enlarge theoperation dynamic range of the FD portion.

FIG. 8 is a schematic plan view of an example of the configuration ofthe amplification type solid-state imaging device according to a firstembodiment of the present invention. Note that components having commonfunctions with those of the circuits shown in FIG. 1 will be explainedassigned the same notations for convenience.

This solid-state imaging device is an example of a configurationoutputting an imaging signal by an analog signal and comprises asemiconductor chip 1 on which a pixel portion 2 having a large number ofunit pixels arranged in a two-dimensional array, a timing generatorportion 3 for generating various types of timing signals, a line memoryportion (column area) 4A for storing analog pixel signals of each pixelrow from the pixel portion 2, a horizontal drive portion 5 for selectingand driving the line memory portion 4A in the horizontal direction, avertical drive portion 6 for selecting and driving each pixel row, andan output amplifier portion 51 etc. for performing predetermined signalprocessing with respect to the pixel signals read out from the pixelportion 2 and outputting the same are formed.

Further, this semiconductor chip 1 is supplied with, as the digitalpower supply system serving as the first power supply system, a firstdigital power supply voltage (DVDD1) from a power supply terminal 45, afirst digital ground voltage (DVSS1) from a power supply terminal 46, asecond digital power supply voltage (DVDD2) from a power supply terminal47, a second digital ground voltage (DVSS2) from a power supply terminal48, a third digital power supply (DVDD3) from a power supply terminal49, and a third digital ground voltage (DVSS3) from a power supplyterminal 50.

Further, the semiconductor chip 1 is supplied with, as the analog powersupply system serving as the second power supply system, a first analogpower supply voltage (AVDD1) from a power supply terminal 40, a firstanalog ground voltage (AVSS1) from a power supply terminal 41, a secondanalog power supply voltage (AVDD2) from a power supply terminal 42, anda second analog ground voltage (AVSS2) from a power supply terminal 43.

Note that the semiconductor chip 1 is provided with a substrate contact(VSUB) 44.

In such a circuit configuration, the pixel portion 2, the line memoryportion 4A, and the output amplifier portion 51 are the analog circuitportions driven by the second power supply system, that is, the analogpower supply, while the TG portion 3, the vertical drive portion 6, andthe horizontal drive portion 5 are the digital circuit portions drivenby the first power supply system, that is, the digital power supply.

In such a solid-state imaging device, along with the successivegenerations of the semiconductor process, the used power supply voltagebecomes smaller. For example, 3.3V in the 0.35 μm process, 2.5V in the0.25 μm process, and 1.8V in the 0.18 μm process.

In the present embodiment, a plurality of power supplies havingdifferent power supply voltage values are supplied from the outside ofthe semiconductor chip 1.

Namely, in FIG. 8, DVDD1 is not equal to DVDD2. For example whenDVDD1=3.3V, DVDD2=2.5V. By supplying such a power supply voltage valuefrom the outside of the solid-state imaging device to the semiconductorchip 1, in particular complete transfer of the signal charge from thephotodiode 23 becomes possible.

Further, the analog power supply voltage values AVDD1 and AVDD2 can beused at different voltages also. By setting the power supply of thepixel portion 2 as AVDD1 and setting the power supply of the line memoryportion 4A and the output amplifier portion 51 as AVDD2, setting theoptimum power consumption for each portion of the circuit becomespossible.

By this, the operating margin of each portion is enlarged, and the powerconsumption of the analog portion can be reduced.

FIG. 9 is a schematic plan view of an example of the configuration of anamplification type solid-state imaging device according to a secondembodiment of the present invention. Note that components having commonfunctions with those of the circuits shown in FIG. 1 will be explainedassigned the same notations for convenience.

This solid-state imaging device is an example of a configuration forconverting an imaging signal to a digital signal, processing thatdigital signal, and outputting the result and comprises a semiconductorchip 1 on which a pixel portion 2 having a large number of unit pixelsarranged in a two-dimensional array, a timing generator portion 3 forgenerating various types of timing signals, an output column portion(column area) 4 such as a column CDS or column AD, a horizontal driveportion 5 for selecting and driving this output column portion 4 in thehorizontal direction, a vertical drive portion 6 for selecting anddriving each pixel row, a signal processing portion (DSP) 7 forprocessing the pixel signals read out from the pixel portion 2, abooster circuit 52 for boosting the analog power supply voltage servingas the second power supply voltage and the digital power supply voltageserving as the first power supply voltage from the outside, and anegative power supply generation circuit 53 etc. for generating anegative power supply by the analog power supply voltage and digitalpower supply voltage from the outside formed thereon.

This semiconductor chip 1 is supplied with, as the digital power supplysystem serving as the first power supply system, a digital power supplyvoltage (DVDD) from a power supply terminal 8 and a digital groundvoltage (DVSS) from a power supply terminal 9 and is supplied with, asthe analog power supply system serving as the second power supplysystem, an analog power supply voltage (AVDD) from a power supplyterminal 10 and an analog ground voltage (AVSS) from a power supplyterminal 11.

Note that the semiconductor chip 1 is provided with a substrate contact(VSUB) 44.

In the present embodiment, both of the digital power supply voltage(DVDD) and the analog power supply voltage (AVDD) 10 have the same powersupply voltage value. By boosting the power supply voltages of AVDD=DVDDat the booster circuit 52 and further generating the negative powersupply by the negative power supply generation circuit 53, another powersupply voltage value is generated inside the semiconductor chip 1.

In this way, even if there is a single power supply voltage valuesupplied from the outside of the semiconductor chip 1, by generating aplurality of power supply voltages inside the chip, the operating marginof the pixel portion 2 can be greatly enlarged.

Further, as a result of this, change of the threshold value Vth of thetransistor, which is usually selectively set at the ion implantationmask, becomes unnecessary, so it becomes possible to greatly reduce thenumber of masks at the ion implantation work.

FIG. 10 is a schematic plan view of an example of the configuration ofan amplification type solid-state imaging device according to a thirdembodiment of the present invention. Note that components having commonfunctions with those of the circuits shown in FIG. 1 will be explainedassigned the same notations for convenience.

This solid-state imaging device is an example of a configurationmodifying the configuration of the first embodiment shown in FIG. 8 todigital output and further performing digital signal processing andcomprises a semiconductor chip 1 on which a pixel portion 2 having alarge number of unit pixels arranged in a two-dimensional array, atiming generator portion 3 for generating various types of timingsignals, an output column portion (column area) 4 such as a column CDSor column AD, a horizontal drive portion 5 for selecting and drivingthis output column portion 4 in the horizontal direction, a verticaldrive portion 6 for selecting and driving each pixel row, a signalprocessing portion (DSP) 7 for processing the pixel signals read outfrom the pixel portion 2, etc. formed thereon.

Further, this semiconductor chip 1 is supplie with, as the digital powersupply system serving as the first power supply system, the firstdigital power supply voltage (DVDD1) from the power supply terminal 45,the first digital ground voltage (DVSS1) from the power supply terminal46, the second digital power supply voltage (DVDD2) from the powersupply terminal 47, the second digital ground voltage (DVSS2) from thepower supply terminal 48, the third digital power supply (DVDD3) fromthe power supply terminal 49, and the third digital ground voltage(DVSS3) from the power supply terminal 50.

Further, the semiconductor chip 1 is supplied with, as the analog powersupply system serving as the second power supply system, the firstanalog power supply voltage (AVDD1) from the power supply terminal 40,the first analog ground voltage (AVSS1) from the power supply terminal41, the second analog power supply voltage (AVDD2) from the power supplyterminal 42, and the second analog ground voltage (AVSS2) from the powersupply terminal 43.

Note that the semiconductor chip 1 is provided with a subtrate contact(VSUB) 44.

Also, in this third embodiment, by supplying a plurality of powersupplies having different power supply voltage values from the outsideof the semiconductor chip 1, the operating margin of the circuit isenlarged and further it becomes possible to optimize the powerconsumption of each circuit block.

Next, an explanation will be given of an example of the configurationsof the unit pixel of the pixel portion 2 explained above and thevertical drive portion 6 for driving the same as a fourth embodiment ofthe present invention.

FIG. 11 is a block diagram of an example of the configuration of theunit pixel and the vertical drive portion in the fourth embodiment ofthe present invention.

As mentioned above, the pixel portion 2 is provided with a large numberof unit pixels 55 in a two-dimensional array. Each unit pixel 55 in thepresent example is configured by a photodiode 23, a transfer transistor(transfer gate TG) 18, a charge detection unit (FD portion) 17, anamplifier transistor 56, an analog power supply terminal (AVDD1) 40, aselection (address) transistor 57, a vertical signal line 59, etc.

Further, the vertical drive portion 6 for driving the pixel portion 2 isconfigured by a vertical register portion 64 for sequentially selectingpixel rows in the vertical direction and level shifter circuits 61, 62,63. etc. for shifting the levels of the selection signals by thisvertical register portion 64 by the power supply voltage.

The level shifter circuits 61, 62, and 63 control the gate voltages ofthe selection transistor 57, the reset transistor 16, and the transfergate 18 and apply a control pulse ΦR (for reset), ΦTG (for transfergate), and ΦA (for selection) to the transistors of the unit pixel 55.

In the example of FIG. 11, a voltage larger than the power supplyvoltage DVDD1 must be applied to the transfer gate 18 and the selectiontransistor 57, so a power supply voltage DVDD2 larger than the DVDD1 issupplied by the level shifter circuits 61 and 63.

In this way, the configuration of the vertical drive portion 6 becomescomplex, but a voltage difference between the power supply voltage andthe GND voltage is big, so the operating margin of the pixel can be madelarge.

As a result, change of the threshold value Vth of the transistor, whichis usually selectively set at the ion implantation mask, becomesunnecessary, so it becomes possible to greatly reduce the number ofmasks at the ion implantation work.

FIGS. 12A to 12C are timing charts of the operation timings of thecontrol pulses shown in FIG. 11. The pulse ΦA applied to the selectiontransistor 57 is made the voltage of DVDD2 (DVDD2>DVDD1). By doing this,the channel voltage of the selection transistor 57 can be made largerthan the power supply voltage DVDD1. Thereafter, a pulse ΦR=DVDD1 isapplied to the reset transistor 16. By this, the charge detection unit17 can be reset.

The charge detection unit 17 must be completely reset up to the samepotential as that of the power supply voltage AVDD1 of the pixel portion2, so becomes a threshold voltage which can be completely reset even ifΦR=DVDD1 in this figure (also ΦR can use the DVDD2, but the case notusing this was shown in FIGS. 12A to 12C). Thereafter, by applyingΦTG=DVDD2 to the transfer gate 18, the signal charge of the photodiode23 can be read out to the charge detection unit 17.

FIG. 13 is a cross-sectional view of the stack structure of the pixelportion 2 of the embodiment shown in FIG. 11.

As illustrated, the silicon substrate 12 has a P-well 13 formed on it.This P well 13 has an element isolation area (LOCOS element isolation inthe present example, but sometimes ST1 etc.) 14, a power supply area(AVDD) 15, a reset gate (Reset) 16 of the reset transistor, a chargedetection unit 17, a transfer gate (TG) 18 for transferring the signalcharge of the photodiode 23 to the charge detection unit 17, a P+ typelight receiving layer 19, and an N-type photo-electric conversion layer20 etc. forming the photodiode 23 formed on it.

The charge detection unit 17 is connected to the gate of the amplifiertransistor 56 via the contact 17A etc., and the power supply area 15 isconnected to the first analog power supply terminal (AVDD1) 40 via thecontact 15A etc.

FIG. 14 to FIG. 18 are explanatory views of the potential levelscorresponding to the cross-sectional view shown in FIG. 13, wherein theordinates correspond to the potential level (V), and the abscissascorrespond to the locations for forming the elements on the substratesurface of FIG. 4. Note that components common with those of FIG. 3 toFIG. 7 which have been already explained are assigned the samenotations.

First, the power supply voltage (AVDD1) of the pixel portion 2 in thepresent example is 1.8V in this figure (indicated by 26 in the figure).

Further, in FIG. 14, the transfer gate 18 and the reset transistor 16become ΦTG=ΦR=“OFF” state. A signal charge (Qsig) 24 is stored in thearea of the photodiode 23.

Next, FIG. 15 shows the potential level in the state where ΦTG=“OFF” andΦR=“ON”. Here, the charge detection unit (FD portion) 17 is set at 1.8Vby the power supply voltage AVDD1 of the pixel portion.

Next, FIG. 16 shows the potential level in the state where ΦTG=“OFF” andΦR=“OFF”. Here, by turning OFF the reset transistor 16, the potential ofthe charge detection unit 17 fluctuates. This is the influence of theparasitic capacitance between the gate of the reset transistor 16 andthe charge detection unit 17.

Next, FIG. 17 shows the potential level in the state where ΦTG=“ON” andΦR=“OFF”. The voltage of ΦTG=“ON”=DVDD2 is larger than DVDD1. In thiscase, DVDD2 becomes equal to 2.5V (>DVDD1).

Accordingly, the voltage applied to the transfer gate 18 is large, so itbecomes possible to completely read out the signal charge (Qsig) 24 ofthe photodiode 23 to the charge detection unit 17.

Next, FIG. 18 shows the potential level in the state where ΦTG=“OFF” andΦR=“OFF”.

As described above, in the present embodiment, by using a voltage largerthan the power supply voltage AVDD1=DVDD1 of the pixel portion 2, forexample ΦTG=“ON”=DVDD2, it becomes possible to completely transfer thesignal charge of the photodiode 23.

FIG. 19 is a block diagram of an example of the configurations of theunit pixel and the vertical drive portion in a fifth embodiment of thepresent invention.

This fifth embodiment has a configuration supplying power supplyvoltages of a plurality of levels from the outside and has a pixelconfiguration different from that of the fourth embodiment of FIG. 11explained above.

The components of each unit pixel 55 are, in the same way as the fourthembodiment, the photodiode 23, the transfer transistor 18, the amplifiertransistor 56, the selection transistor 57, the reset transistor 16,etc., but the connection configuration is different.

Further, the vertical drive portion 6 is comprised of a verticalregister portion 64, two level shifter circuits 65 and 66, etc.

FIGS. 20A to 20C are timing charts of the operation timings of controlpulses shown in FIG. 19.

In order to activate the selection transistor 57, ΦR=“ON”=DVDD1 (=AVDD1)is applied.

By this, the selection transistor is activated, and its pixel isselected (in actuality, a plurality of pixels are arranged in the rowdirection, so all pixels in the row direction are activated).

Thereafter, the reset transistor 16 is activated. That is, ΦR=DVDD1 isapplied, and the charge detection unit 17 is reset to the power supplyvoltage (AVDD1) of the pixel portion 2.

Next, a pulse is applied to the transfer gate 18. Namely, by settingΦTG=“ON”=DVDD2>DVDD1, it becomes possible to completely transfer thesignal of the photodiode 23 to the charge detection unit 17.

Further, by using a plurality of power supply voltages, the number oftypes of the threshold values Vth of the transistors used in the pixelportion 2 can be reduced to one, and reduction of the number of masksbecomes possible.

FIG. 21 is a block diagram of an example of the configurations of theunit pixel and the vertical drive portion in a sixth embodiment of thepresent invention.

This sixth embodiment has a configuration supplying a single powersupply voltage from the outside in the same way as the second embodimentof FIG. 9 mentioned above and shows a case of the configuration offorming the booster circuit 52 inside the chip and generating aplurality of power supply voltages.

Then, the unit pixel 55 is comprised of a photodiode 23, a transfer gate18, a charge detection unit 17, an amplifier transistor 56, a resettransistor 16, a selection transistor 57, etc. Further, the verticaldrive portion 6 is configured by a vertical register portion 64, levelshifter circuits 71, 72, and 73, and a booster circuit 52 for supplyingpower supplies to the level shifter circuits 71, 72, and 73.

Further, four control signals of a Φp pulse 67, ΦR pulse 22, ΦTG pulse21, and ΦA pulse 60 are supplied from the level shifter circuits 71, 72,and 73 for driving the unit pixels.

FIGS. 22A to 22E are timing charts of the operation timings of thecontrol pulses shown in FIG. 21.

FIG. 23 to FIG. 28 are explanatory views of the potential levels in thepresent embodiment, wherein the ordinates correspond to the potentiallevel (V), and the abscissas correspond to the location for forming eachelement on the substrate surface. Note that components common to thoseof FIG. 3 to FIG. 7 which have been already explained are assigned thesame notations.

In the circuit of FIG. 21, a first state corresponds to FIG. 22A andFIG. 23.

Next, the booster circuit 52 is activated. By this, the booster circuit52 operates, and boost-up voltages (DVDD1) 68, (DVDD2) 69, and (DVDD3)70 are generated. That is, it corresponds to FIG. 22B and FIG. 24.

At this time, the voltage of a drain end 74 of the reset transistor 16is VD. Next, the power supply voltage (DVDD2) is applied to the pulse(ΦA) 60 for selecting the selection transistor 57. Pixels are activatedby this.

Next, the power supply voltage (DVDD1) is applied to the pulse (ΦR) 22for selecting the reset transistor 16. FIG. 22C and FIG. 25 correspond.By this, the voltage of the charge detection unit 17 is set at theboost-up voltage DVDD3=VD. That is, this means that the charge detectionunit 17 is reset to the boosted voltage DVDD3.

Next, the pulse (ΦR) 22 selected by the reset transistor 16 is made“OFF”. This corresponds to FIG. 22D and FIG. 26.

Thereafter, the power supply voltage DVDD1 is applied to the transfergate (TG) 18. This corresponds to FIG. 22E and FIG. 27. Due to this, thesignal charge (Qsig) 24 of the charge detection unit 18 is read out tothe charge detection unit 18. At this time, the voltage of the chargedetection unit 18 is large, so the amount of the read signal charge canbe made large. That is, it is possible to enlarge the dynamic range ofthe signal.

Further, as indicated by a broken line area 75 in FIG. 27, it ispossible to obtain a punch through effect by a large drain field, socomplete transfer becomes easy. That is, even if the power supplyvoltage (AVDD1) of the pixel becomes small, by using the presentembodiment, it becomes possible to completely read out the signal chargeof the photodiode.

The transfer gate (TG) 18 is made “OFF”. This corresponds to FIG. 22Fand FIG. 28.

FIG. 29 is a block diagram of an example of the configuration of theunit pixels in a seventh embodiment of the present invention, and FIGS.30A to 30F are timing charts of operation timings of the control pulsesshown in FIG. 29. In FIG. 29, the unit pixel 55 is comprised of aphotodiode 23, a transfer gate 18, a charge detection unit 17, anamplifier transistor 56, a reset transistor 16, a selection transistor57, etc.

The drain end of the amplifier transistor 56 is connected to the powersupply voltage (AVDD1) 40 of the unit pixel 55, and the drain end of thereset transistor 16 is connected to the control line (Φp) 76.

Next, an explanation will be given of the operation of the unit pixel 55by using FIGS. 30A to 30F.

First, it is switched from the state of ΦR1=“H” and Φp=“H” (secondstate) to Φp=“H”→“L”) (first state). Thereafter, ΦR2=“L”→“H” and thepulse are applied. By this, the gate voltage (VG) of the resettransistor 16 rises from the ground potential GND.

Next, ΦR1 is made equal to “H”→“L”, and then Φp is made equal to“L”→“H”. By doing this, by coupling of the parasitic capacitance of thegate (VG) and the drain end (Φp) of the reset transistor 16, the gatevoltage of the reset transistor rises and can be made DVDD1 or more. Dueto this, the potential VFD of the charge detection unit 17 can be resetto DVDD1.

This is a method capable of completely resetting the charge detectionunit 17 by the power supply voltage even if a booster circuit 52 or adepletion type transistor is not used and advantageous for the reductionof the number of masks etc.

FIG. 31 is a block diagram of an example of the configuration of theunit pixels in an eighth embodiment of the present invention, and FIGS.32A to 32E are timing charts of the operation timings of the controlpulses shown in FIG. 31.

In FIG. 31, the unit pixel 55 is comprised of a photodiode 23, atransfer gate 18, a charge detection unit 17, an amplifier transistor56, a reset transistor 16, a selection transistor 57, etc.

In the present embodiment, the sequence of analog power supply voltageterminal (AVDD1) 40→selection transistor 57→amplifier transistor56→vertical signal line 59 is important. Below, this operation timingwill be explained by using FIGS. 32A to 32E.

First, in a state where the pixel is not activated, the reset transistor16 is made “ON”. Then, the potential VFD of the charge detection unit 17is set to the power supply DVDD1. In this example, DVDD1=AVDD1, so thevoltage VFD of the charge detection unit 17 becomes the power supplyvoltage of the pixel.

Next, in order to activate the selection transistor 57, ΦA is applied.By this, the voltage Vn of the node 84 is boosted from 0V tointermediate voltage. The node 84 and the charge detection unit 17 arecoupled by the parasitic capacitance, and the charge detection unit 17is in the floating state, so the VFD of the charge detection unit 17 isboosted to a voltage larger than DVDD1 as indicated by 86 in FIG. 32E.

In this way, by making the timing 87 for reset earlier than the timing88 for selecting the pixel, the potential VFD of the charge detectionunit 17 can be boosted.

This can be realized by just the means of the drive timing, sotransistors having different threshold values do not have to be used,and the booster circuit may be kept small.

FIG. 33 is a block diagram of an example of the configuration of theunit pixels in a ninth embodiment of the present invention.

In the above eighth embodiment, as indicated by 83 in FIG. 32C, avoltage when not applying a pulse to the transfer gate was defined asthe negative voltage (DVSS3). By this, a leakage current flowing intothe photodiode during a storage period can be suppressed.

Accordingly, in the ninth embodiment, a concrete means for realizing thenegative voltage as mentioned above will be explained.

For example, level shift circuits 80 and 81 etc. as shown in FIG. 31have the structure shown in FIG. 33.

Namely, this level shift circuit has an inverter portion (transistors 89and 92) receiving signals from the vertical register portion 64 and acircuit (transistors 90, 91, 93, and 94) for shifting the voltage on theGND side after that from DVSS1 (=0V) to DVSS2 (<0V).

By such a circuit configuration, if a negative voltage is applied to theDVDD2, when this level shift circuit is “OFF”, the “negative voltage”will be applied to the transfer gate pulse ΦTG to the pixel portion 2.

FIG. 34 is a schematic cross-sectional view of a concrete example of thestack structure of such a level shift circuit. As illustrated, in thepixel portion 2 on the silicon substrate 12, a sensor P-well area 98 isformed overall, and a sensor P-well voltage (AVSS1) is applied.

Further, an N-well area 99 is formed so as to surround the periphery ofthis sensor P-well area 98, and a second P-well area 100 is formedoutside of the same. Then, this second P-well area 100 is supplied withDVSS2 by the contact 104, and the overall P-well voltage becomes anegative voltage.

In this P-well area 100, a portion (transistors 93 and 94) of a brokenline frame 106 shown in FIG. 33 will be formed.

Further, the outside of the second P-well area 100 is formed with anN-well area 101 and is formed with a substrate contact 44.

Note that a further outside peripheral circuit portion is formed by anN-well area 103 and a P-well area 102 etc., and the DVSS1 is applied tothe P-well area 102 by a contact 105. By such a structure, it becomespossible to form a well structure for applying a negative voltage to thepixel portion 2.

Concrete examples of the configurations of the present invention wereexplained above, but the present invention can be widely employed inamplification type solid-state imaging devices (CMOS image sensors)having other structures as well. Very effective technology can beprovided especially in the case of reducing the voltage.

As explained above, according to the solid-state imaging device of thepresent invention, since a plurality of power supply voltages were inputfrom the outside and the plurality of power supply voltages wereselectively supplied to the pixel portion and the peripheral circuitportion, by using the plurality of power supply voltages, setting theoptimum power consumption for each portion becomes possible and,especially, the analog power supply voltage required for the pixelportion can be effectively set, so there are the effects that theoperating margin of each portion is enlarged, the power consumption ofthe analog portion including the pixel portion can be reduced, andfurther it becomes possible to achieve complete transfer of the signalcharge in the pixel portion.

Further, change of the threshold value Vth of the transistor, which isusually selectively set by the ion implantation mask, becomesunnecessary, so there is the effect that the number of masks at the ionimplantation work can be greatly reduced and shortening of the processsteps can be realized.

Further, according to the solid-state imaging device of the presentinvention, a plurality of power supply voltages were generated from thepower supply voltage from the outside by using the level shifting means,and the plurality of power supply voltages were selectively supplied tothe pixel portion and the peripheral circuit portion, therefore, byusing a plurality of power supply voltages, setting the optimum powerconsumption for each portion becomes possible, and especially the analogpower supply voltage required for the pixel portion can be effectivelyset, so there are the effects that the operating margin of each portionis enlarged, the power consumption of the analog portion including thepixel portion can be reduced, and further it becomes possible to achievecomplete transfer of the signal charge in the pixel portion.

Further, change of the threshold value Vth of the transistor, which isusually selectively set at the ion implantation mask, becomesunnecessary, so there is the effect that the number of masks at the ionimplantation work can be greatly reduced, and shortening of the processsteps can be realized.

INDUSTRIAL APPLICABILITY

The solid-state imaging device of the present invention can set theoptimum power consumption for each portion by using a plurality of powersupply voltages and especially can effectively set the second powersupply voltage required for the pixel portion, therefore the operatingmargin of each portion is enlarged, the power consumption of the analogportion including the pixel portion can be reduced, and further itbecomes possible to achieve complete transfer of the signal charge inthe pixel portion, so it is possible to maintain a good image qualityand can be applied to an imaging device such as a digital camera.

1. A solid-state imaging device having a pixel portion comprised of aplurality of unit pixels and a peripheral circuit portion forcontrolling the pixel portion, wherein the peripheral circuit portionoperates with a first power supply voltage of a first power supplysystem and the pixel portion operates with a second power supply voltageof a second power supply system having a value different from that ofthe first power supply voltage, said solid-state imaging devicecomprising: a first power supply inputting portion for receiving asinput the first power supply voltage of the first power supply systemfrom the outside and a second power supply inputting portion forreceiving as input the second power supply voltage from the outside andsupplying the same to the pixel portion; a column area for storingsignals of each pixel row adjoining said pixel portion; a level shiftingunit for converting a level of said first power supply voltage andsupplying a power supply voltage generated by said level shifting unitto a predetermined location; characterized in that: said unit pixel hasat least a photo-electric conversion unit generating a signal charge inaccordance with an amount of light received, a charge detection unit foracquiring a signal charge generated by said photoelectric conversionunit, a transferring unit for transferring a signal charge generated bysaid photoelectric conversion unit to said charge detection unit, aresetting unit for resetting said photo-electric conversion unit, and anamplifying unit for converting a signal charge of said charge detectionunit to an electric signal and outputting it to an output signal line,and said level shifting unit supplies a level shifted power supplyvoltage to the transferring unit and resetting unit.
 2. A solid-stateimaging device as set forth in claim 1, characterized in that said levelshifting unit supplies a power supply voltage value to the transferringmeans set higher than the power supply voltage value for supplying tosaid resetting unit.
 3. A solid-state imaging device having a pixelportion comprised of a plurality of unit pixels and a peripheral circuitportion for controlling the pixel portion, wherein the peripheralcircuit portion operates with a first power supply voltage of a firstpower supply system and the pixel portion operates with a second powersupply voltage of a second power supply system having a value differentfrom that of the first power supply voltage, said solid-state imagingdevice comprising: a first power supply inputting portion for receivingas input the first power supply voltage of the first power supply systemfrom the outside and a second power supply inputting portion forreceiving as input the second power supply voltage from the outside andsupplying the same to the pixel portion; further comprising a verticaldrive portion for driving said pixel portion, a source of a resettransistor forming a resetting unit connected to a charge detectionunit, and a drain of said reset transistor controlled by a verticaldrive portion.
 4. A solid-state imaging device as set forth in claim 3,characterized in that a drain control line is supplied with a thirdpower supply voltage during a period other than the read period of thesignal charge and is supplied with a fourth power supply voltage higherthan said third power supply voltage during the read period of thesignal charge, the fourth power supply voltage is used for reset of saidcharge detection unit and a series of read operations including readingof the signal charge, and the applied voltage of said drain control lineis returned to said third power supply voltage after the end of the readoperation of said signal charge.
 5. A solid-state imaging device as setforth in claim 3, characterized in that a thickness of a gate insulationfilm of each transistor of said pixel portion is larger than a thicknessof a gate insulation film of transistors at the peripheral circuitportion other than said pixel portion.
 6. A solid-state imaging deviceas set forth in claim 3, further comprising a control transistor forcontrolling a gate of said reset transistor to a floating state, holdinga gate of said reset transistor at a second state to set it at a firstvoltage when said drain control line is a first state, then setting saiddrain control line to a second state to set the gate of the resettransistor to a second voltage larger than the first voltage bycapacitance coupling.
 7. A solid-state imaging device as set forth inclaim 6, characterized in that said unit pixel further comprises aselection transistor for selecting a pixel row, Sets said resettransistor to the ON state to set said charge detection unit to thefirst voltage, sets said reset transistor to the OFF state to set saidcharge detection unit to a floating state, then sets said selectiontransistor to the ON state so as to boost said charge detection unit tothe second voltage by the parasitic capacitance of the source of saidselection transistor and said charge detection unit.
 8. A solid-stateimaging device as set forth in claim 6, characterized in that said unitpixel further comprises a selection transistor for selecting a pixelrow, each said unit pixel has at least one power supply voltage source,a connection order in each unit pixel is the power supply voltagesource, selection transistor, amplification transistor, and outputsignal line, and the order of driving said pixel portion is first toturn said reset transistor ON once, then turn said selection transistorON so as to read out a signal charge of said photo-electric conversionunit.
 9. A solid-state imaging device having a pixel portion comprisedof a plurality of unit pixels and a peripheral circuit portion forcontrolling the pixel portion, wherein the peripheral circuit portionoperates with a first power supply voltage of a first power supplysystem and the pixel portion operates with a second power supply voltageof a second power supply system having a value different from that ofthe first power supply voltage, said solid-state imaging devicecomprising: a first power supply inputting portion for receiving asinput the first power supply voltage of the first power supply systemfrom the outside and a second power supply inputting portion forreceiving as input the second power supply voltage from the outside andsupplying the same to the pixel portion; a column area for storingsignals of each pixel row adjoining said pixel portion; at least one ofsaid first and second power supply voltages is a negative power supplyvoltage; and further wherein a pixel portion area of the semiconductorsubstrate is formed with a first well area of a first conductivity type,the outer circumference is formed with a second well area of a secondconductivity type, and a further outer circumference is formed with athird well area of the first conductivity type, and said third well areais supplied with a negative power supply voltage, the inside of saidthird well area is formed with an n-channel insulating gate type fieldeffect transistor, and a source of said n-channel insulating gate typefield effect transistor and said third well area are made the samenegative power supply voltage.
 10. A solid-state imagine device having apixel portion comprised of a plurality of unit pixels and a peripheralcircuit portion for controlling the pixel portion, wherein theperipheral circuit operates with a first power supply voltage and thepixel portion operates with a second power supply voltage having a valuedifferent from that of the first power supply voltage, said solid-stateimaging device comprising: a power supply inputting portion forreceiving as input a power supply voltage of a single level from theoutside and a level shifting unit for converting the level of the powersupply voltage received as input by the power supply inputting portionto the first power supply voltage and/or second power supply voltage,wherein the first rower supply voltage generated by the level shiftingunit is selectively supplied to the peripheral circuit portion, and thegenerated second power supply voltage is selectively supplied to thepixel portion said unit pixel has at least a photo-electric conversionunit generating a signal charge in accordance with an amount of lightreceived, a charge detection unit for acquiring a signal chargegenerated by said photo-electric conversion unit, a transferring unitfor transferring a signal charge generated by said photoelectricconversion unit to said charge detection unit, a resetting unit forresetting said photo-electric conversion unit, and an amplifying unitfor converting a signal charge of said charge detection unit to anelectric signal and outputting it to an output signal line, and saidlevel shifting unit supplies a level shifted power supply voltage to thetransferring unit and resetting unit.
 11. A solid-state imaging deviceas set forth in claim 10, characterized in that said level shifting unitsupplies a power supply voltage value for supplying to the transfer ringunit set higher than the power supply voltage value for supplying tosaid resetting unit.
 12. A solid-state imaging device having a pixelportion comprised of a plurality of unit pixels and a peripheral circuitportion for controlling the pixel portion, wherein the peripheralcircuit operates with a first power supply voltage and the pixel portionoperates with a second power supply voltage having a value differentfrom that of the first power supply voltage, said solid-state imagingdevice comprising: a power supply inputting portion for receiving asinput a power supply voltage of a single level from the outside and alevel shifting unit for converting the level of the power supply voltagereceived as input by the power supply inputting portion to the firstpower supply voltage and/or second power supply voltage, wherein thefirst power supply voltage generated by the level shifting unit isselectively supplied to the peripheral circuit portion, and thegenerated second power supply voltage is selectively supplied to thepixel portion further comprising a vertical drive portion for drivingsaid pixel portion, a source of a reset transistor forming saidresetting unit connected to said charge detection unit, and a drain ofsaid reset transistor controlled by said vertical drive portion.
 13. Asolid-state imaging device as set forth in claim 12, characterized inthat said drain control line is supplied with a third power supplyvoltage during a period other than the read period of the signal chargeand is supplied with a fourth power supply voltage higher than saidthird power supply voltage during the read period of the signal charge,the fourth power supply voltage is used for reset of said chargedetection unit and a series of read operations including reading of thesignal charge, and the applied voltage of said drain control line isreturned to said third power supply voltage after the end of the readoperation of said signal charge.
 14. A solid-state imaging device as setforth in claim 12, characterized in that a thickness of a gateinsulation film of each transistor of said pixel portion is larger thana thickness of a gate insulation film of transistors at the peripheralcircuit portion other than said pixel portion.
 15. A solid-state imagingdevice as set forth in claim 12, characterized by further comprising acontrol transistor for controlling a gate of said reset transistor to afloating state, holding a gate of said reset transistor at a secondstate to set it at a first voltage when said drain control line is afirst state, then setting said drain control line to a second state toset the gate of the reset transistor to a second voltage larger than thefirst voltage by capacitance coupling.
 16. A solid-state imaging deviceas set forth in claim 15, characterized in that said unit pixel furthercomprises a selection transistor for selecting a pixel row, sets saidreset transistor to the ON state to set said charge detection unit tothe first voltage, sets said reset transistor to the OFF state to setsaid charge detection unit to a floating state, then sets said selectiontransistor to the ON state so as to boost said charge detection unit tothe second voltage by the parasitic capacitance of the source of saidselection transistor and said charge detection unit.
 17. A solid-stateimaging device as set forth in claim 15, characterized in that said unitpixel further comprises a selection transistor for selecting a pixelrow, each said unit pixel has at least one power supply voltage source,a connection order in each unit pixel is the power supply voltagesource, selection transistor, amplification transistor, and outputsignal line, and the order of driving said pixel portion is first toturn said reset transistor ON once, then turn said selection transistorON so as to read out a signal charge of said photo-electric conversionunit.
 18. A solid-state imaging device having a pixel portion comprisedof a plurality of unit pixels and a peripheral circuit portion forcontrolling the pixel portion, wherein the peripheral circuit operateswith a first power supply voltage and the pixel portion operates with asecond power supply voltage having a value different from that of thefirst power supply voltage, said solid-state imaging device comprising:a power supply inputting portion for receiving as input a power supplyvoltage of a single level from the outside and a level shifting unit forconverting the level of the power supply voltage received as input bythe power supply inputting portion to the first power supply voltageand/or second power supply voltage, wherein the first power supplyvoltage generated by the level shifting unit is selectively supplied tothe peripheral circuit portion, and the generated second power supplyvoltage is selectively supplied to the pixel portion; at least one ofsaid plurality of power supply voltages is a negative power supplyvoltage; and a pixel portion area of the semiconductor substrate isformed with a first well area of a first conductivity type, an outercircumference is formed with a second well area of a second conductivitytype, and a further outer circumference is formed with a third well areaof the first conductivity type, and said third well area is suppliedwith a negative power supply voltage, the inside of said third well areais formed with an n-channel insulating gate type field effecttransistor, and a source of said n-channel insulating gate type fieldeffect transistor and said third well area are made the same negativepower supply voltage.